Metadata-Version: 2.1
Name: sv-simpleparser
Version: 0.3.0
Summary: Easy-To-Use SystemVerilog Parser
Keywords: SystemVerilog,Verilog,Parser
Author-Email: Eric Macedo <ericsmacedo@gmail.com>
Classifier: Programming Language :: Python :: 3
Classifier: Programming Language :: Python :: 3.10
Classifier: Programming Language :: Python :: 3.11
Classifier: Programming Language :: Python :: 3.12
Classifier: Programming Language :: Python :: 3.13
Classifier: Operating System :: OS Independent
Project-URL: Homepage, https://github.com/ericsmacedo/sv-simpleparser
Project-URL: Documentation, https://sv-simpleparser.readthedocs.io/en/stable/
Project-URL: Bug Tracker, https://github.com/ericsmacedo/sv-simpleparser/issues
Requires-Python: <4.0,>=3.10.0
Requires-Dist: click>=8.2.1
Requires-Dist: pygments>=2.19.1
Requires-Dist: jinja2>=3.1.6
Requires-Dist: pydantic>=2.11.5
Requires-Dist: rich>=14.0.0
Description-Content-Type: text/markdown

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# Easy-To-Use SystemVerilog Parser

* [Documentation](https://sv-simpleparser.readthedocs.io/en/stable/)
* [PyPI](https://pypi.org/project/sv-simpleparser/)
* [Sources](https://github.com/ericsmacedo/sv-simpleparser)
* [Issues](https://github.com/ericsmacedo/sv-simpleparser/issues)

## Features

* Extract Port Lists
* Extract Parameters
* Extract Submodule Instances
* `ifdef` support (planned)
* Standards: `IEEE 1800-2009 SystemVerilog`

## Limitations

* No Syntax Checks - Source Code files must be syntactically correct
* No Full Parser - This parser intends to be simple and just extract some information from the source code. Fast and easy.

## Installation

Installing it is pretty easy:

```bash
pip install sv-simpleparser
```
